Compositional static instruction cache simulation
نویسندگان
چکیده
منابع مشابه
Fast instruction cache analysis via static cache simulation
This paper introduces a new method for instruction cache analysis that outperforms conventional tracedriven methods. The new method, static cache simulation, analyzes a program for a given cache configuration and determines prior t o execution time if an instruction reference will always result in a cache hit or miss. At run time, counters are incremented to provide the execution frequency of p...
متن کاملStatic Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reducing the access energy substantially at the cost of certain performance degradation. Here, the energy-delay product reduction heavily depends on the prediction accuracy of the predictor. In this paper, a simplified patte...
متن کاملStatic cache simulation and its applications
This work takes a fresh look at the simulation of cache memories. It introduces the technique of static cache simulation that statically predicts a large portion of cache references. To e ciently utilize this technique, a method to perform e cient on-they analysis of programs in general is developed and proved correct. This method is combined with static cache simulation for a number of applica...
متن کاملPOWER2 instruction cache unit
Introduction IBM introduced the POWER-based RISC System/6000@ (RS/6000) workstation in February of 1990. This system was well received in the industry and helped IBM capture a sizable share of the workstation market. The POWER2TM processor goals were to build on the strengths of the original POWER design and to overcome its shortcomings. The POWER and POWER2 systems partition instruction proces...
متن کاملSecond - level Instruction Cache Thread Processing Unit Thread Processing Unit Thread Processing Unit Instruction Cache First - level First - level First - level Instruction Cache Instruction Cache Execution
This paper presents a new parallelization model, called coarse-grained thread pipelining, for exploiting speculative coarse-grained parallelism from general-purpose application programs in shared-memory multiprocessor systems. This parallelization model, which is based on the ne-grained thread pipelining model proposed for the superthreaded architecture 11, 12], allows concurrent execution of l...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ACM SIGPLAN Notices
سال: 2004
ISSN: 0362-1340,1558-1160
DOI: 10.1145/998300.997183